The present invention relates to analog-to-digital converter testing and, more particularly, to an apparatus and method having an efficient data transfer scheme.
During production, analog-to-digital converters (ADCs) are tested by checking whether various performance parameters of the ADC or device under test meet respective specifications. Two commonly measured performance parameters of ADCs during production testing are differential nonlinearity (DNL) and integral nonlinearity (INL). Various ways of measuring these performance parameters are described in xe2x80x9cLinearity testing issues of analog to digital converters,xe2x80x9d T. Kuyel, IEEE International Test Conference, pp. 747-756, 1999 which is incorporated by reference herein.
The fastest known method for testing embedded analog to digital converters (ADCs) is the histogram-testing method which refers to a method of collecting multiple data points per code step and then calculating INL, DNL, and code transitions. It is described in xe2x80x9cTutorial DSP-Based Testing of Analog and Mixed-signal Circuits,xe2x80x9d M. Mahoney, (1987) which is incorporated by reference herein.
A typical test flow includes an analog level forced to an ADC input. The input signal, a voltage which increases linearly in time from a given minimum value to a given maximum value, is applied. The ADC takes a sample of the input signal at given instants and converts the sample into a code word on the outputs of the converter. The time, xcex94t, elapsing between two successive samples determines how often the ADC takes a sample of the input signal in conformity with the sampling frequency, fsample=1/xcex94t. In order to achieve accurate testing of the ADC with respect to the DNL and the INL, the number of samples per code word should be sufficiently large. A practical example involves the testing of a 12-bit ADC with a sampling frequency fsample of 400 KHz, the tester being arranged to take 64 samples per code word. Generally, the outputs of the ADC generate a signal which increases linearly in time in discrete steps, following the input signal. Each discrete step yields a digital code word.
Due to imperfections of ADCs, the output signal deviates from the ideal output signal. Measurement of the signal by a tester offers a characterization of the quality of the ADC. The width of the steps is a measure of the relevant DNL of the ADC. A further parameter, the INL represents the difference between the expected transition point of the outputs and the actual transition point. The INL for a given point can also be determined by summing the individual values of the DNL per step up to the relevant point. The measurement is also suitable for determining the offset of the ADC by measuring the width of the first step, step 000, by determining the voltage when the converter outputs the first code word larger than 0.
A conventional automatic test system for testing semiconductors includes a workstation, a handling device, a test body and a test mainframe. The test mainframe includes at least one sequencer control module and a digital mainframe board having a digital pattern memory. The handling device is coupled to the workstation. At the workstation, a user can provide a pattern file to be stored in the digital pattern memory. The sequencer control module coupled with the digital pattern memory and clocking information provides the control signals to the test body for controlling a sequence of vectors applied to the device under test. In addition, it provides control signals received by the handling device for maneuvering the device under test to come in direct contact with the test probes located on the test body. The device under test, such as an analog-to-digital converter, responsive to the sequence of vectors generates n-bit code word outputs for each test signal. These code words are stored in a digital capture memory located in the test body. A communication channel links the workstation, the handling device, the test body and the test mainframe together for transferring control signals and data. The test mainframe sends control signals to the test body to send each n-bit code word corresponding to each test signal sample. The data is processed in a digital signal processor residing in the test mainframe to build a histogram and to calculate both the DNL and INL for the device under test. This entire process is repeated for thousands of conversions. The data accumulated from each conversion is used to determine whether the device under test has met pre-determined criteria for functionality.
In many commercial testers, transferring data from the digital capture memory to the tester memory is a very slow process. Moreover, the histogram testing method requires that hundreds of codes and thousands of conversions be collected to obtain reasonably accurate results which further aggravates the memory transfer problem. Often memory transfer accounts for more than 50% of the DNL and INL test time. For example, to estimate the DNL and INL of a 12-bit ADC with 400K samples per second conversion rate, 95000 samples must be transferred from digital capture memory to the tester memory. The memory transfer time for the 95000 samples is 198 ms on an Advanced Mixed-Signal Test System such as the model A580 sold by TERADYNE(copyright), Inc. If the INL and DNL tests are to be performed at three different supply voltages, the overall memory transfer time will be 594 ms. Assuming 5 cents per second test cost, this translates to a test cost of approximately 3 cents per device. Such high test cost for merely transferring data is unacceptable for large volume production testing.
In addition, an increased level of resolution of an ADC results in an increase in the number of transition levels to be measured and imposes greater demands on the accuracy of these measurements of INL and DNL. The measurement time required to achieve this level of accuracy will thus increase by a factor of four for each additional bit. As a result, the total time required to exhaustively test an ADC will increase by a factor of eight for each additional bit of resolution.
In an alternate approach, known as hardware histograming, a field programming gate array (FPGA) is attached to a device interface board (DIB). The FPGA is programmed to generate a histogram. The histogram data is stored in a memory chip such as a static random access memory (SRAM) on the DIB. The histogram data is much smaller in comparison to the ADC output data. Hence, it can be transferred to the tester memory very fast. Although this technique reduces the data transfer time, it has several draw backs. First, synchronizing all the added hardware components like FPGAs, SRAMs etc. with the tester and the device under test is an arduous task. Incorporating such a technique to the current production testing will require extensive engineering time. Second, the additional hardware components added on to the test circuitry are prone to failures. Hence additional test codes must be written and frequently executed for verifying the functionality of the added test hardware.
Another approach is defined in U.S. Pat. No. 5,854,598, filed Oct. 4, 1996, by De Vries et. al., which is incorporated by reference herein. The method taught includes a step of reconstructing the relevant code word on the basis of the number of least-significant bits of the relevant code word and the value of the test signal corresponding to the relevant code word. This method and apparatus, however, necessitates the addition of a low-pass filter to eliminate the toggling of the least significant bit due to noise inherent in the system by passing the signal of this bit through the low-pass filter. This solution adds a delay to the testing sequence which is undesirable. More importantly, the post filtering solution provides an inaccurate translation of the relevant code word at the region where the toggling of the least significant bit arises due to noise. Thus, DNL and INL calculated using the reconstructed code word according to this approach will be inaccurate in the presence of noise. Although this approach may give sufficiently accurate DNL and INL for an approximate evaluation of embedded ADCs within large systems, it cannot be used for production testing of stand-alone ADCs. Stand-alone ADCs, such as those sold as catalog products, require accurate measurement of DNL and INL during production testing.
For the foregoing reasons, there is an urgency for development of an efficient memory transfer technique for ADC testing which increases the speed of data transfer from the digital capture memory to the tester memory. This new technique, however, should not require extensive modification to the existing test flow so that the engineering cost in implementing the modification is minimal.
The testing system and method described herein reduces the production test time of analog to digital converters (ADCs). More specifically, the apparatus method in accordance with the present invention reduces the data transfer time between the digital capture memory located in the test body and the tester memory located in the test mainframe. The test system includes a workstation, a handling device, a test body and a test mainframe. The handling device is coupled to the workstation and test mainframe. A user may supply through the workstation input to trigger the test mainframe to provide control signals to the test body such that a sequence of vectors are applied to the device under test. In addition, control signals may be sent to the handling device for maneuvering the device under test to come in direct contact with the test probes located on the test body. The device under test, in particular, an analog-to-digital converter, responsive to the sequence of vectors generates n-bit code word outputs for each test signal.
A communication channel links the workstation, the handling device, the test body and the test mainframe together for transferring control signals and data. The test mainframe sends control signals to the test body to send a m-bit packet of least significant bits for each n-bit code word, where m is less than n. In the alternative, a user at the workstation can activate the sequencer control module to send control signals to the test body to send a m-bit packet for each n-bit code word where m is proportional to the noise amplitude inherent in the system in terms of least significant bits. The test mainframe calculates the number of m-bit packets that can simultaneously be transferred over the communications channel to the test mainframe. Once the test mainframe captures this data in a test memory, the test mainframe regenerates the original n-bit code word from this m-bit packetized data by determining an offset value to add to each m-bit packet to sum to the value of the original n-bit code word. The test mainframe further processes n-bit code words to determine whether the device passes a predetermined criteria of operability.